In modern electronic circuits, such as, for example, input/output (IO) buffers, it is desirable to control the relative variation between pull-up and pull-down impedances of the IO buffers for a variety of reasons, including, but not limited to, transmission line matching, minimizing switching noise (e.g., di/dt), optimizing signal swing, etc. In many high-speed, high-bandwidth applications, such as, for example, memory interfacing (e.g., double data rate 3 (DDR3) or DDR4 memory), it is particularly important to control pull-up and pull-down impedances of an interface circuit in such a way that the relative difference between the pull-up and pull-down impedances (i.e., impedance mismatch) is minimized. For example, one Joint Electron Devices Engineering Council (JEDEC) standard requires impedance mismatch in an output driver circuit to be within ten percent (10%) over variations in integrated circuit (IC) process, supply voltage and/or temperature (PVT) conditions to which the circuit may be subjected.
In order to achieve such tight control of impedance variation and pull-up/pull-down impedance mismatch, a buffer, often referred to as a compensated buffer, is typically employed which is adapted to compensate for variations in PVT conditions. In one implementation, a PVT compensated buffer utilizes a compensation circuit including a PVT control block which monitors a deviation in output impedance of a block of one or more reference devices matched to corresponding devices (e.g., drivers) in an output stage of the buffer to be compensated. The PVT control block generates a set of digital bits, often referred to as “PVT bits,” that are used to control the reference devices (e.g., by turning the devices on or off) to thereby maintain a substantially constant output impedance. The output impedance of the reference block will be a function of the number of devices in the block that are turned on or off at any given time. These PVT bits are also fed to the buffer for controlling the output impedance of the buffer output stage devices in a corresponding manner. The number of drivers in the buffer output stage is directly proportional to the number of digital control bits.
In the context of metal-oxide-semiconductor (MOS) transistor devices, since p-channel MOS (PMOS) transistor devices and n-channel MOS (NMOS) transistor devices do not generally track one another, pull-up devices, which typically employ PMOS transistors, will generally exhibit a different characteristic spread compared to pull-down devices, which typically employ NMOS transistors. In smaller IC fabrication technologies (e.g., 28 nanometers (nm)), the spread between PMOS and NMOS device characteristics, and correspondingly impedance mismatch, is often exacerbated.